1. Field of the Invention
The present invention generally relates to a synchronous semiconductor memory device which operates in synchronism with an external clock signal, and, more particularly, to a synchronous semiconductor memory device such as a pipeline burst SRAM in which the reading/writing of a plurality of data is performed.
2. Description of the Background Art
FIG. 12 is a block diagram showing a pipeline burst SRAM which is a former synchronous semiconductor memory device. In the figure, reference numeral 101 designates an address buffer for outputting to an address resistor 102 a plurality of address signals SA inputted from the outside, and address signals /SA obtained from the address signals SA. Reference numeral 102 designates an address register for holding the address signals SA and /SA inputted through the address buffer 101, and outputting the address signals SA and /SA to a decoder 106 in synchronism with a SAC clock signal (hereinafter referred to as SACCLK signal). Reference numeral 103 designates an address buffer for outputting externally inputted lowermost place address signals SA0 and SA1 to a counter 105.
104 is a counter enabling signal generator (ADV State Machine) for generating a counter enabling signal (hereinafter referred to as ADVCLK signal) synchronizing with an external clock signal. More particularly, the generator 104 generates the ADVCLK signal on the basis of a CE signal generated from external signals SE1, SE2, and SE3#, and the SACCLK signal, and outputting the ADVCLK signal to the counter 105. The generator 104, upon the inputting of a signal for data reading purpose (having a state in which the SACCLK signal takes an "H" value and the CE signal takes an "H" value), generates a ADVCLK signal in synchronism with an external clock signal input next to that generated at the time of the inputting of the data reading purpose signal. In addition, a similar ADVCLK signal is also generated when a signal for data writing purpose is inputted.
Reference numeral 105 designates a counter for outputting the lowermost place address signals inputted from the outside in synchronism with the SACCLK signal to the decoder 106, and outputting to the decoder 106 address signals corresponding to the lowermost place address signals in response to the ADVCLK signal generated in the counter enabling signal generator 104. Reference numeral 106 designates a decoder for generating instructions for data reading/writing or the like for the addresses obtained from the addresses outputted from the counter 105 and the address outputted from the address register 102.
Reference numeral 107 designates an SRAM core capable of information (data) reading or writing. The SRAM core 107 reads out data from a specified address or writes data to the specified address, in response to the instruction generated by the decoder 106.
Reference numeral 108 designates an output register for holding the data transmitted from the SRAM core 107 via a data bus RD, and outputting these data to an output buffer 110 in synchronism with the external clock signal. Reference numeral 109 designates an output enabling signal generator (OE State Machine) for outputting to an output buffer 110 as well as to an input buffer 111 an output enabling signal (hereinafter referred to as OE signal) synchronizing with the external clock signal generated on the basis of the external signal CE and the SACCLK signal. Reference numeral 110 designates an output buffer for outputting data transmitted from the output register 108 to the outside in response to the OE signal.
Reference numeral 111 designates an input buffer for taking from outside data to be inputted to the SRAM core 107 upon receipt of the OE signal. Reference numeral 112 designates an input register for holding data input from the outside through the input buffer 111, and inputting the holding data to the SRAM core 107 in synchronism with the external clock signal.
Now, the operation of the former synchronous semiconductor memory device is described.
In a case of an operation for reading out data at a specified address to the outside from the SRAM core 107, the signal for data reading purpose (hereinafter referred to as read signal) is input from the outside. (That is, data is read out when SACCLK, SGW#, and CE obtained from SE1, SE2, and SE3# becomes signals for reading.) The pulse of the external clock signal at the time of the inputting of the read signal is named as the 1st pulse, and the pulses subsequently generated by the external clock signal are named as the 2nd pulse, the 3rd pulse hereunder.
When such read signal is externally inputted, the counter enabling signal generator circuit 104 generates an ADVCLK signal having three pulses respectively synchronizing with the 2nd, 3rd, and 4th pulses of the external clock signal, and outputs the ADVCLK signal to the counter 105.
Upon the inputting of the read signal, the counter 105 outputs to the decoder 106, the lowermost place address signals input from the outside in synchronism with the SACCLK signal consisting of a pulse synchronized with the 1st pulse of the external clock signal. The counter 105 also sequentially outputs the addresses corresponding the lowermost address signals to the decoder 106 in synchronism with the pulse of the ADVCLK signal. Through such operation of the counter 105, in response to one read signal for data reading purpose, four mutually related addresses are sequentially sent to the decoder 106 in synchronism with the external clock signal.
The decoder 106 determines memory selection lines in the SRAM core 107 according tb the address signals inputted from the counter 105 and the address signals inputted from the address register 102, and sends an instruction to the SRAM core 107 for reading the data stored at locations corresponding to the selection lines. The SRAM core 107 responds to such instruction to output the data stored at the corresponding locations to the output resistor 108 via the data bus RD.
The output register 108 outputs the data inputted via the data bus RD to the output buffer 110 in synchronism with the external clock signal. The output buffer 110 outputs the data held in the output register 108 to the outside in response to the OE signal.
In the former memory device, the OE signal is generated in the output enabling signal generator circuit 109 in response to the read signal or the signal for data writing purpose (hereinafter referred to as write signal) so as to be in synchronism with a predetermined external clock signal.
In a data writing operation, data inputted from the outside (i.e., from DINDOUT terminal) in response to a write signal is inputted to the input register 112, which inputs the data to the SRAM core 107 in synchronism with the external clock signal. In this operation, a location for writing is inputted in a manner similar to that described in the above reading operation, whereby the above data is made to be written to this location.
In this specification, the symbol "/" represents the negative value of a signal as /A means the negative value of a signal A. Particularly, "#" is used instead of "/" with regard to the terminal of a synchronous semiconductor memory device.
The former synchronous semiconductor memory device constructed as described above, for one read signal, sequentially outputs data corresponding to an external address and a plurality of addresses relative to the external address. Similarly, the former device, for one write signal, continuously takes data corresponding to an external address and a plurality of addresses according to the external address.
The former synchronous semiconductor memory device outputs (or takes) data regarding to a plurality of related addresses for one read (or write) signal even in a test operation. In other wards, the former device cannot outputs (or takes) data only solely relating to a single address. Thus, data regarding only an individual address cannot be directly tested in the former device. As a result, there may arise a problem in which a test between two data at two addresses cannot be performed except for data to be continuously outputted, whereby the defect in such portion cannot be checked.
Further, since the former synchronous semiconductor memory device operates very differently from a general-purpose memory such as an asynchronous SRAM in which only data corresponding to one address is outputted (or inputted) for one read signal (or write signal), the test pattern and the test method which have been used in the test of the general-purpose memory cannot be used as well as the test method used for the general-purpose memory cannot be used. As a result, there also arises a problem that a test between given data cannot be readily performed.
In addition, the output buffer 110 outputs data to the outside in response to the OE signal generated by the output enabling signal generator 109 within the synchronous semiconductor memory device. The input buffer ill also takes data from the outside upon receipt of the OE signal generated in the output enabling signal generator 109 within the synchronous semiconductor memory device. Accordingly, even in a test operation, the data exchange between the outside and the inside of the synchronous semiconductor memory device is always synchronized with the external clock signal, which results in a problem that the outputting or inputting of data for a desired period of time with a desired timing cannot be performed.